Shakti Platform Board Support Package
Introduction
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Arty A7-35T/100T Boards |
Arty A7-35T/100T Pinout |
Arty A7-35T/100T Pmod Pinout |
This board support package (BSP) supports Shakti Pinaka and Vajra soft processor cores implemented through Digilent Arty A7-35T and Arty A7-100T FPGA boards.
· This BSP is based on driver APIs developed by Shakti Processor Development Team. Dated: 01.06.2021. Link: https://gitlab.com/shaktiproject/software/shakti-sdk
· It uses xPack GNU RISC-V Embedded GCC Version 8.3.0-2020.04.1 compiler tool chain for generating required binaries. Link: https://xpack.github.io/riscv-none-embed-gcc.
· Memory configuration file version Pinaka-21042021, Vajra-21042021.
· Supports uploading generated binary to FPGA RAM and flash memory.
Getting Started
· Install Digilent driver software from OEM on Windows host system. For convenience this driver software is provided in the drivers folder of CASP installation directory. With this driver user can program FPGA board with bit stream and MCS files from Xilinx Vivado Software. Digilent driver software actually installs FTDI driver for communicating with Arty FPGA board via USB port.
· CASP uses OpenOCD tool to upload Shakti hex files to Arty FPGA RAM. OpenOCD software further relies on libusbK driver for uploading. User can download and install libusbK driver. This driver is also provided in the drivers folder of CASP installation directory. If user is installing the driver from CASP installation directory then manual driver installation method shall be adopted as no exe file is provided to automate this process. User has to right click of the device -> Select Update Driver -> Browse my computer for drivers -> Let me pick from the list.... -> Have Disk -> Browse to the driver folder and choose Digilent_USB_Device_(Interface_0).inf file to install the driver. User may further refer to Microsoft documentation on how to install a driver manually.
· These two drivers are required for different scenarios i.e.
§ For uploading MCS and binary files to FPGA flash from Vivado Software, FTDI driver is required
§ For uploading the generated hex file to FPGA RAM, libusbK driver is required.
§ However, any of the above two drivers can be used for serial communication via USB Virtual COM port from CASP.
· Following procedure may be adopted to use appropriate driver
§ Reconnect FPGA board. Goto device manager window.
§ In Windows Device Manager, FPGA board USB chip exposes three interfaces (devices)
§ Device 0 - is shown as USB Serial Converter A with FTDI driver and as Digilent USB Device (Interface 0) with libusbK driver.
§ Device 1 - is shown as USB Serial Converter B
§ Device 2 - is shown as USB Serial Port (COMxx)
§ To switch between FTDI and libusbK drivers, right click on the Device 0 (appears as one of the two devices mentioned above based on the installed driver) -> Update Driver -> Browse my computer for device software -> Let me pick from a list... and choose required driver from one of the two Device 0 drivers mentioned above.
· Install Xilinx Vivado Software. It is required for uploading MCS file and CASP generated binary file to Arty FPGA flash memory.
· Download Shakti processors soft core MCS file from Shakti Development Team official web site and refer corresponding documentation on how to upload MCS file. Upload MCS file to Arty FPGA flash memory.
· Create model and build to generate required binary.
· Refer below for programming and debugging support.
Shakti Pinaka Arty A7-35T Configuration
· General Configuration
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Configuration Parameter |
Parameter Value |
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Board Title |
Shakti Pinaka Arty35 |
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Tool Chain Type |
Local Build |
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Board Preprocessor Symbol |
_BUILD_BRD_SHAKTI_PINAKA |
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Platform Preprocessor Symbol |
_BUILD_PLT_RISCV_SHAKTI |
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Compiler Preprocessor Symbol |
_BUILD_CMP_RISCV_GCC |
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C++11 Standard Support |
No |
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File System Support |
No |
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OpenMP/OpenCL/CUDA Support |
No/No/No |
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Simulation Panel Support |
No |
· Hardware Configuration
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Configuration Parameter |
Parameter Value |
Remarks |
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Number of CPU cores |
1 |
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Dynamic Memory Support |
Yes |
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Prefer Fixed/Floating Point |
Floating Point |
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DI/DO Pins |
IO0 (RX1)[0], IO1 (TX1)[1], IO2 (RX2)[2], IO3 (PWM0) (TX2)[3], IO4[4], IO5 (PWM1)[5], IO6 (PWM2)[6], IO7[7], IO8[8], IO9 (PWM3)[9], IO10 (PWM4) (SPI1-CS)[10], IO11 (PWM5) (SPI1_MOSI)[11], IO12 (SPI1_MISO)[12], IO13 (SPI1_CLK)[13], JB3[14], JB4[15], LED4[16], LED5[17], LED6[18], LED7[19], BTN0[20], BTN1[21], BTN2[22], BTN3[23], JD1[24], JD2[25], JD3[26], JD4[27], JD7[28], JD8[29], JD9[30], JD10[31] |
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ADC Default Resolution |
12 |
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ADC Pins |
ADC0[0x250], ADC1[0x254], ADC2[0x258], ADC3[0x25C], ADC4[0x27C], ADC5[0x240], ADC6_7[0x270], ADC8_9[0x274], ADC10_11[0x278] |
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PWM Default Resolution |
12 |
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PWM Pins |
IO3 (PWM0) (TX2)[0], IO5 (PWM1)[1], IO6 (PWM2)[2], IO9 (PWM3)[3], IO10 (PWM4) (SPI1-CS)[4], IO11 (PWM5) (SPI1_MOSI)[5] |
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DAC Default Resolution |
0 |
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DAC Pins |
- |
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UART0 |
Via USB Programmer Port |
- Implemented through TargetHw_Serial block. - By default UART Rx interrupt is enabled. User may change these settings in shakti.h file located in BSP directory. - Works only when the program is uploaded to flash instead on RAM |
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UART1 Pins |
IO0(RX), IO1(TX) |
- Implemented through TargetHw_Serial1 block - By default UART Rx interrupt is enabled. User may change these settings in shakti.h file located in BSP directory. |
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UART2 Pins |
IO2(RX), IO3(TX) |
- Implemented through TargetHw_Serial2 block - By default UART Rx interrupt is enabled. User may change these settings in shakti.h file located in BSP directory. |
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SPI Pins |
IO10(CS), IO11(MOSI), IO12(MISO), IO!3(CLK) |
Implemented through SPI1 interface of Shakti driver. Refer SPI.h from BSP directory. Also SPI0 of Shakti is implemented through SPI1. |
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I2C Pins |
SDA, SCL |
Implemented through I2C1 interface of Shakti driver. Refer Wire.h from BSP directory |
Shakti Vajra Arty A7-100T Configuration
· General Configuration
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Configuration Parameter |
Parameter Value |
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Board Title |
Shakti Vajra Arty100 |
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Tool Chain Type |
Local Build |
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Board Preprocessor Symbol |
_BUILD_BRD_SHAKTI_VAJRA |
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Platform Preprocessor Symbol |
_BUILD_PLT_RISCV_SHAKTI |
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Compiler Preprocessor Symbol |
_BUILD_CMP_RISCV_GCC |
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C++11 Standard Support |
No |
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File System Support |
No |
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OpenMP/OpenCL/CUDA Support |
No/No/No |
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Simulation Panel Support |
No |
· Hardware Configuration
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Configuration Parameter |
Parameter Value |
Remarks |
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Number of CPU cores |
1 |
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Dynamic Memory Support |
Yes |
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Prefer Fixed/Floating Point |
Floating Point |
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DI/DO Pins |
IO0 (RX1)[0], IO1 (TX1)[1], IO2 (RX2)[2], IO3 (PWM0) (TX2)[3], IO4[4], IO5 (PWM1)[5], IO6 (PWM2)[6], IO7[7], IO8[8], IO9 (PWM3)[9], IO10 (PWM4) (SPI1-CS)[10], IO11 (PWM5) (SPI1_MOSI)[11], IO12 (SPI1_MISO)[12], IO13 (SPI1_CLK)[13], JB3[14], JB4[15], LED4[16], LED5[17], LED6[18], LED7[19], BTN0[20], BTN1[21], BTN2[22], BTN3[23], JD1[24], JD2[25], JD3[26], JD4[27], JD7[28], JD8[29], JD9[30], JD10[31] |
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ADC Default Resolution |
12 |
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ADC Pins |
ADC0[0x250], ADC1[0x254], ADC2[0x258], ADC3[0x25C], ADC4[0x27C], ADC5[0x240], ADC6_7[0x270], ADC8_9[0x274], ADC10_11[0x278] |
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PWM Default Resolution |
12 |
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PWM Pins |
IO3 (PWM0) (TX2)[0], IO5 (PWM1)[1], IO6 (PWM2)[2], IO9 (PWM3)[3], IO10 (PWM4) (SPI1-CS)[4], IO11 (PWM5) (SPI1_MOSI)[5] |
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DAC Default Resolution |
0 |
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DAC Pins |
- |
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UART0 |
Via USB Programmer Port |
Implemented through TargetHw_Serial block. Works only when the program is uploaded to flash instead on RAM |
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UART1 Pins |
IO0(RX), IO1(TX) |
Implemented through TargetHw_Serial1 block |
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UART2 Pins |
IO2(RX), IO3(TX) |
Implemented through TargetHw_Serial2 block |
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SPI Pins |
IO10(CS), IO11(MOSI), IO12(MISO), IO!3(CLK) |
Implemented through SPI1 interface of Shakti driver. Refer SPI.h from BSP directory |
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I2C Pins |
SDA, SCL |
Implemented through I2C1 interface of Shakti driver. Refer Wire.h from BSP directory |
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Ethernet |
Supported |
Implemented through TargetHw_Swadeshi block |
Programmer
CASP supports two programmers for uploading generated binary file
1. Programmer0 can be used for uploading hex file to Arty FPGA RAM. It uses OpenOCD tools to upload the hex.
2. Programmer1 can be used for uploading binary file to Arty FPAG flash memory via Xilinx Vivado Software Interface. For this Xilinx Vivado installation path needs to be updated in Programmer1 Executable Path in CASP Target Hardware Settings as shown in below figure
Debugging
Debugging via USB virtual serial COM port is supported. To enable serial port debugging set ‘Code Debug Level’ to Level3 from Setup Simulation->Build tab. Debugging is possible only when the program is uploaded to FPGA flash instead on RAM.
Known Issues & Limitations
· This BSP is presently work in progress.
· Shakti SPI hardware works in a bit different way with respect to other commercial implementations. As such users are advices to use SPI.send() and SPI.receive() methods instead of SPI.transfer() method of CASP HAL API..
· Currently, Shakti core only supports high level interrupts for GPIOs. However, CASP supports positive edge trigger interrupts through software. As such CASP GPIO interrupts works best below 500Hz.
· Using constant variables in class constructor is having issues