Vega Platform Board Support Package
Introduction
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Arty A7-35T/100T Boards |
Arty A7-35T/100T Pinout |
Arty A7-35T/100T Pmod Pinout |
This board support package (BSP) supports CDAC-Vega Theja32 soft processor core implemented through Digilent Arty A7-35T FPGA board.
· This BSP is based on driver APIs developed by Vega Processor Development Team. Dated: 01.06.2021. Link: https://gitlab.com/cdac-vega/vega-sdk
· It uses xPack GNU RISC-V Embedded GCC Version 8.3.0-2020.04.1 compiler tool chain for generating required binaries. Link: https://xpack.github.io/riscv-none-embed-gcc.
· Memory configuration file used for Thejas32 is from CDAC-Vega team dated: Nov, 2020.
· Supports uploading generated binary to FPGA RAM and flash memory.
Getting Started
· Install Digilent driver software from OEM on Windows host system. For convenience this driver software is provided in the drivers folder of CASP installation directory. With this driver user can program FPGA board with bit stream and MCS files from Xilinx Vivado Software. Digilent driver software actually installs FTDI driver for communicating with Arty FPGA board via USB port.
· Install Xilinx Vivado Software. It is required for uploading MCS file and CASP generated binary file to Arty FPGA flash memory.
· Download Vega processors soft core MCS and Bit files from CDAC-Vega Development Team official web site and refer corresponding documentation on how to upload MCS file. Upload MCS file to Arty FPGA flash memory.
· Create model and build to generate required binary.
· Refer below for programming and debugging support.
Vega Thejas32 Arty A7-35T Configuration
· General Configuration
Configuration Parameter |
Parameter Value |
Board Title |
Vega Thejas32 Arty35 |
Tool Chain Type |
Local Build |
Board Preprocessor Symbol |
_BUILD_BRD_VEGA_THEJAS32 |
Platform Preprocessor Symbol |
_BUILD_PLT_RISCV_VEGA |
Compiler Preprocessor Symbol |
_BUILD_CMP_RISCV_GCC |
C++11 Standard Support |
No |
File System Support |
No |
OpenMP/OpenCL/CUDA Support |
No/No/No |
Simulation Panel Support |
No |
· Hardware Configuration
Configuration Parameter |
Parameter Value |
Remarks |
Number of CPU cores |
1 |
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Dynamic Memory Support |
Yes |
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Prefer Fixed/Floating Point |
Floating Point |
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DI/DO Pins |
IO2 (GPIO0)[0], IO3 (GPIO1)[1], IO4 (GPIO2)[2], IO26 (GPIO3)[3], IO27 (GPIO4)[4], IO28 (GPIO5)[5], IO29 (GPIO6)[6], IO30 (GPIO7)[7], IO31 (GPIO8)[8], IO32 (GPIO9)[9], IO33 (GPIO10)[10], IO34 (GPIO11)[11], IO35 (GPIO12)[12], IO36 (GPIO13)[13], IO37 (GPIO14)[14], IO38 (GPIO15)[15], LED0_R (GPIO19)[19], LED0_G (GPIO20)[20], LED0_B (GPIO21)[21], LED1_R (GPIO22)[22], LED2_G (GPIO23)[23], LED2_B (GPIO24)[24], LED5 (GPIO16)[16], LED6 (GPIO17)[17], LED7 (GPIO18)[18], BTN0 (GPIO25)[25], BTN1 (GPIO26)[26], BTN2 (GPIO27)[27], BTN3 (GPIO28)[28], SW0 (GPIO29)[29], SW1 (GPIO30)[30], SW2 (GPIO31)[31] |
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ADC Default Resolution |
12 |
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ADC Pins |
ADC0[0x14], ADC1[0x15], ADC2[0x16], ADC3[0x17] |
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PWM Default Resolution |
12 |
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PWM Pins |
IO5 (PWM0)[0], IO6 (PWM1)[1], IO7 (PWM2)[2], IO8 (PWM3)[3], IO9 (PWM4)[4], IO39 (PWM5)[5], IO40 (PWM6)[6], IO41 (PWM7)[7] |
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DAC Default Resolution |
0 |
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DAC Pins |
- |
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UART0 |
Via USB Programmer Port |
Implemented through TargetHw_Serial block. Works only when the program is uploaded to flash instead on RAM |
UART1 Pins |
IO0(RX), IO1(TX) |
Implemented through TargetHw_Serial1 block |
UART2 Pins |
PMOD-A 2(RX), 3(TX) |
Implemented through TargetHw_Serial2 block |
SPI, SPI1 and SPI2 Pins |
See figure above for SPI pins. Any GPIO pin can be used for SPI chip select (CS) pin. |
Implemented through SPI0, SPI1 and SPI2 interfaces of Vega driver respectivily. Refer SPI.h from BSP directory |
I2C Pins |
SDA, SCL |
Implemented through I2C1 interface of Vega driver. Refer Wire.h from BSP directory |
Programmer
CASP supports two programmers for uploading generated binary file
1. Programmer0 can be used for uploading hex file to Arty FPGA RAM. It uses OpenOCD tools to upload the hex.
2. Programmer1 can be used for uploading binary file to Arty FPAG flash memory via Xilinx Vivado Software Interface. Xilinx Vivado installation path needs to be updated in Programmer1 Executable Path in CASP Target Hardware Settings as shown in below figure. This process requires bit stream file i.e. thejas_32.bit to be available in project directory.
Debugging
Debugging via USB virtual serial COM port is supported. To enable serial port debugging set ‘Code Debug Level’ to Level3 from Setup Simulation->Build tab. Debugging is possible only when the program is uploaded to FPGA flash instead on RAM.
Known Issues & Limitations
· This BSP is presently work in progress.
· Currently, Vega core only supports high level interrupts for GPIOs. However, CASP supports positive edge trigger interrupts through software. As such CASP GPIO interrupts works best below 200Hz.
· User may experience some inconsistency in Vega interrupts.
· Using constant variables in class constructor is having issues.