Board Support Package For Xilinx FPGA Development Boards
Introduction
|
Digilent Arty S7 |
Digilent Arty A7 |
|
This board support package (BSP) supports Digilent Arty-S7-50T, A7-35T & 100T and Z7-20 Boards with Xilinx 7 FPGAs. The BSP is based on Xilinx Vitis HLS Compiler software tool for generating required RTL from a user created CASP model. On Xilinx Z7 platform this BSP targets programmable logic (PL) part of the SoC, processing system (PS) part is available in separate BSP.
Getting Started
· Install Xilinx Vivado and Vitis software tools along with Digilent drivers.
· It is recommended to use one of the template projects (based on the selected target) available at /hardware/xilinx/fpga directory. Accordingly, open CASP project named ‘CaspHlsDefault’ available in one of the template project directory. Modify the model as required and build to generate required RTL as an IP. If user creates a project at any other location, then the RTL path shall be manually specified in Xilinx Vivado IP Catalogue for importing the RTL into the Vivado Design.
· Follow the documentation available in above mentioned project for further instruction on how to generate final bit stream file. Also, refer to individual board documentation from Digilent website for details about individual board.
Board Configuration
· General Configuration
|
Configuration Parameter |
Arty S7-50T |
Arty A7-35T |
Arty A7-100T |
Arty Z7-20 |
|
Board Title |
ArtyS7_XC7S50T |
ArtyA7_XC7A35T |
ArtyA7_XC7A100T |
ArtyZ7_XC7Z020_PL |
|
Tool Chain Type |
Local Build |
Local Build |
Local Build |
Local Build |
|
Board Preprocessor Symbol |
_BUILD_BRD_ARTY_XC7S50T |
_BUILD_BRD_ARTY_XC7A35T |
_BUILD_BRD_ARTY_XC7A100T |
_BUILD_BRD_ARTY_XC7Z020_PL |
|
Platform Preprocessor Symbol |
_BUILD_PLT_XC7S |
_BUILD_PLT_XC7A |
_BUILD_PLT_XC7A |
_BUILD_PLT_XC7Z |
|
Compiler Preprocessor Symbol |
_BUILD_CMP_VIVADO_HLS |
_BUILD_CMP_VIVADO_HLS |
_BUILD_CMP_VIVADO_HLS |
_BUILD_CMP_VIVADO_HLS |
|
C++11 Standard Support |
No |
No |
No |
No |
|
Debug Support |
No |
No |
No |
No |
|
File System Support |
No |
No |
No |
No |
|
OpenMP/OpenCL/CUDA Support |
No/No/No |
No/No/No |
No/No/No |
No/No/No |
|
Simulation Panel Support |
No |
No |
No |
No |
· Hardware Configuration
|
Configuration Parameter |
Arty S7-50T |
Arty A7-35T |
Arty A7-100T |
Arty Z7-20 |
|
Number of CPU cores |
- |
- |
- |
- |
|
Dynamic Memory Support |
No |
No |
No |
No |
|
Prefer Fixed/Floating Point |
Fixed Point |
Fixed Point |
Fixed Point |
Fixed Point |
|
DI/DO Pins |
LED0_R[0], LED0_G[1], LED0_B[2], LED1_R[3], LED1_G[4], LED1_B[5], LED2[6], LED3[7], LED4[8], LED5[9], BTN0[10], BTN1[11], BTN2[12], BTN3[13], SW0[14], SW1[15], SW2[16], SW3[17], IO0[18], IO1[19], IO2[20], IO3[21], IO4[22], IO5[23], IO6[24], IO7[25], IO8[26], IO9[27], IO26_JD1[28], IO27_JD2[29], IO28_JD3[30], IO29_JD4[31], IO30_JD7[32], IO31_JD8[33], IO32_JD9[34], IO33_JD10[35], IO34_JC1[36], IO35_JC2[37], IO36_JC3[38], IO37_JC4[39], IO38_JC7[40], IO39_JC8[41], IO40_JC9[42], IO41_JC10[43] |
LED0_R[0], LED0_G[1], LED0_B[2], LED1_R[3], LED1_G[4], LED1_B[5], LED2_R[6], LED2_G[7], LED2_B[8], LED3_R[9], LED3_G[10], LED3_B[11], LED4[12], LED5[13], LED6[14], LED7[15], BTN0[16], BTN1[17], BTN2[18], BTN3[19], SW0[20], SW1[21], SW2[22], SW3[23], IO0[24], IO1[25], IO2[26], IO3[27], IO4[28], IO5[29], IO6[30], IO7[31], IO8[32], IO9[33], IO10[34], IO11[35], IO12[36], IO13[37], IO26[38], IO27[39], IO28[40], IO29[41], IO30[42], IO31[43], IO32[44], IO33[45], IO34[46], IO35[47], IO36[48], IO37[49], IO38[50], IO39[51], IO40[52], IO41[53] |
LED0_R[0], LED0_G[1], LED0_B[2], LED1_R[3], LED1_G[4], LED1_B[5], LED2_R[6], LED2_G[7], LED2_B[8], LED3_R[9], LED3_G[10], LED3_B[11], LED4[12], LED5[13], LED6[14], LED7[15], BTN0[16], BTN1[17], BTN2[18], BTN3[19], SW0[20], SW1[21], SW2[22], SW3[23], IO0[24], IO1[25], IO2[26], IO3[27], IO4[28], IO5[29], IO6[30], IO7[31], IO8[32], IO9[33], IO10[34], IO11[35], IO12[36], IO13[37], IO26[38], IO27[39], IO28[40], IO29[41], IO30[42], IO31[43], IO32[44], IO33[45], IO34[46], IO35[47], IO36[48], IO37[49], IO38[50], IO39[51], IO40[52], IO41[53] |
LED0[6], LED1[7], LED2[8], LED3[9], LED4_R[0], LED4_G[1], LED4_B[2], LED5_R[3], LED5_G[4], LED5_B[5], BTN0[10], BTN1[11], BTN2[12], BTN3[13], SW0[14], SW1[15], IO0[18], IO1[19], IO2[20], IO3[21], IO4[22], IO5[23], IO6[24], IO7[25], IO8[26], IO9[27], IO10[28], IO11[29], IO12[30], IO13[31], IO26[32], IO27[33], IO28[34], IO29[35], IO30[36], IO31[37], IO32[38], IO33[39], IO34[40], IO35[41], IO36[42], IO37[43], IO38[44], IO39[45], IO40[46], IO41[47] |
|
ADC Default Resolution |
12 |
12 |
12 |
12 |
|
ADC Pins |
CH_A0[0], CH_A1[1], CH_A2[2], CH_A3[3], CH_A4[4], CH_A5[5], CH_A6A7[6], CH_A8A9[7], CH_VPVN[8] |
CH_A0[0], CH_A1[1], CH_A2[2], CH_A3[3], CH_A4[4], CH_A5[5], CH_A6A7[6], CH_A8A9[7], CH_A10A11[8] |
CH_A0[0], CH_A1[1], CH_A2[2], CH_A3[3], CH_A4[4], CH_A5[5], CH_A6A7[6], CH_A8A9[7], CH_A10A11[8] |
CH_A0[0], CH_A1[1], CH_A2[2], CH_A3[3], CH_A4[4], CH_A5[5], CH_A6A7[6], CH_A8A9[7], CH_A10A11[8] |
|
PWM Default Resolution |
12 |
12 |
12 |
12 |
|
PWM Pins |
LED0_R[0], LED0_G[1], LED0_B[2], LED1_R[3], LED1_G[4], LED1_B[5], LED2[6], LED3[7], LED4[8], LED5[9] |
LED0_R[0], LED0_G[1], LED0_B[2], LED1_R[3], LED1_G[4], LED1_B[5], LED2_R[6], LED2_G[7], LED2_B[8], LED3_R[9], LED3_G[10], LED3_B[11], LED4[12], LED5[13], LED6[14], LED7[15] |
LED0_R[0], LED0_G[1], LED0_B[2], LED1_R[3], LED1_G[4], LED1_B[5], LED2_R[6], LED2_G[7], LED2_B[8], LED3_R[9], LED3_G[10], LED3_B[11], LED4[12], LED5[13], LED6[14], LED7[15] |
LED0[0], LED1[1], LED2[2], LED3[3], LED4_R[4], LED4_G[5], LED4_B[6], LED5_R[7], LED5_G[8], LED5_B[9] |
|
DAC Default Resolution |
- |
- |
- |
- |
|
DAC Pins |
- |
- |
- |
- |
|
UART0 |
Via USB Programmer Port. Implemented through ‘FPGA Communication’ block |
Via USB Programmer Port. Implemented through ‘FPGA Communication’ block |
Via USB Programmer Port. Implemented through ‘FPGA Communication’ block |
Not supported in PL. Implemented through PS |
|
UART1 Pins |
- |
- |
- |
- |
|
UART2 Pins |
- |
- |
- |
- |
|
UART3 Pins |
- |
- |
- |
- |
|
UART4 Pins |
- |
- |
- |
- |
|
SPI Pins |
- |
- |
- |
- |
|
I2C Pins |
- |
- |
- |
- |
|
Ethernet Support |
No |
Implemented through ‘FPGA Communication’ block |
Implemented through ‘FPGA Communication’ block |
Not supported in PL. Implemented through PS |
Programmer
Not Applicable
Debugging
Debugging is not supported.
Known Issues & Limitations
· This BSP is currently work in progress.