Board Support Package For Xilinx Zynq SoC (PS) Development Boards

Introduction

Digilent Arty Z7

This board support package (BSP) supports Digilent Arty-Z7-20 development board with Xilinx Zynq SoC. The BSP is based on Xilinx Vitis Compiler software tool targeting processing system (PS) part of the SoC, programmable logic (PL) part is available in separate BSP.

Getting Started

·  Install Xilinx Vivado and Vitis software tools along with Digilent drivers.

·  It is recommended to use the template project available in /hardware/xilinx/fpga/XC7Z020_TEMPLATE_PROJ/CaspPS directory. Accordingly, open CASP project named ‘CaspPS’ in the template project directory. Modify the model as required and build to generate required BOOT.bin file. User may create a project at any other location if required.

·  Follow the documentation available in the above mentioned project for further instruction on how to generate final BOOT.bin file and upload to SD card. Also, refer to the board documentation from Digilent website for details about hardware.

·  Refer below for programming and debugging support.

Board Configuration

· General Configuration

Configuration Parameter	Arty Z7-20
Board Title	ArtyZ7_XC7Z020_PS0
Tool Chain Type	Local Build
Board Preprocessor Symbol	_BUILD_BRD_ARTY_XC7Z020_PS
Platform Preprocessor Symbol	_BUILD_PLT_XC7Z
Compiler Preprocessor Symbol	_BUILD_CMP_VITIS_GCC
C++11 Standard Support	No
Debug Support	Yes
File System Support	No
OpenMP/OpenCL/CUDA Support	No/No/No
Simulation Panel Support	No

· Hardware Configuration

Configuration Parameter	Arty Z7-20
Number of CPU cores	2
Dynamic Memory Support	Yes
Prefer Fixed/Floating Point	Floating Point
DI/DO Pins	-
ADC Default Resolution	-
ADC Pins	-
PWM Default Resolution	-
PWM Pins	-
DAC Default Resolution	-
DAC Pins	-
UART0 Pins	Via programmable USB port. Implemented through TargetHw_Serial block
UART1 Pins	-
UART2 Pins	-
UART3 Pins	-
UART4 Pins	-
SPI Pins	-
I2C Pins	-
Ethernet Support	Implemented through TargetHw_LwIP block

Dual Core Usage

The BSP supports dual core feature on Arty-Z7-20. Following points shall be noted while creating models for this platform

· User can create a single model for programming both cores. Each block in a user created model can be assigned to one of the cores. This can be done by entering core index (starting from zero) in ‘Execution Thread’ parameter of ‘_Block Execution’ group under block parameters.

· Two blocks from different cores cannot be connected.

· To exchange data between blocks that are assigned to different cores user may use ‘Shared Memory With HSEM’ block.

· Each core shall be build separately.

· Options for selecting a particular core and other related options are available through target hardware build options as shown below. Please refer to Project Building & Compiling -> Setup Simulation Parameters in CASP documentation on how to invoke Target Hardware Build Options.

· Basic

Entity Name	Description	Default Value
_Select Execution Core	Select current core to build and program the model	Core0 (Single Core Mode)
Shared memory (OCM) address offset	Enter shared memory address offset	0xFFFF0100
Shared memory (OCM) size	Enter shared memory allocated size	0xd000 (53KBytes)

Programmer

CASP supports Programmer0 for uploading generated BOOT.bin file to the SD card.

Debugging

Debugging is supported over USB serial.

Known Issues & Limitations

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