CASP Demonstration Project on Arty Z7-20 PS SoC Board

 

This project demonstrates how to create a CASP model targeted to Processing System (PS) of Xilinx ZYNQ SoC. The Programmable Logic (PL) bit stream file is automatically taken from the project XC7Z020_TEMPLATE_PROJ. Refer the project documentation for input output signal mapping between PS and PL and other details. Target platform selected is Digilent Arty Z7-20 SoC board.

 

Model

For this demonstration three logics are created in the model

·         Analog Blink Logic - using a sine wave generator (with one second period) connected to an on-board LED3.

·         LED ON/OFF Frequency Control Logic - where in two push buttons (PB0 and PB1) are used to control the frequency of the LEDs (LED1 & LED2) blinking alternately.

·         UART/Ethernet Communication Logic – Digital and analog inputs mapped from PL model via shared memory are received and send to remote terminal (PC) through UART or Ethernet communication. Similarly, the data received from the remote terminal is forwarded to PL via shared memory.

 

Block Parameter Settings

User can view the individual block parameter settings by double clicking on each block.

 

Simulation Settings

Following are simulation setup options configured for current project. Settings that are not shown are left to defaults.

 

Work Flow

Pre-requisites:

·         Xilinx Vitis tools and target board drivers shall be installed.

·         Target board should be connected to the host computer.

·         Xilinx Vitis path shall be configured in CASP from CASP Settings -> Goto current board and right click on it -> Select ‘Addl. Board Variables’ option and enter the required path as shown below

 

 

 


 

Procedure:

·         Ensure that the bit stream file path is correctly specified in /hardware/Xilinx/ps/wsp_xc7z020/out/casp_app_sc_template.bit and /hardware/Xilinx/ps/wsp_xc7z020/out/casp_app_dc_template.bit files

·         Build the model by clicking Build/Run button.

·         During the build process casp_app0.elf file is generated in /hardware/xilinx/ps/wsp_xc7z020/out directory. This file combined with the bit stream file from /hardware/xilinx/fpga/XC7Z020_TEMPLATE_PROJ/sam_proj1.runs/impl_1 directory is used to create the final BOOT.bin file in the same directory. If user starts the build process using the Run button then the BOOT.bin is also available in the project directory.

·         If user enters the SD card drive letter in ‘Target Hardware Programmer Port’ parameter under Setup Simulation Parameters (as shown in below figure) then during Run process the BOOT.bin file is automatically copied to the SD card.

·         User may need to disable ‘Suppress Information Messages’ under Simulation Setup -> Build tab to view the normal messages generated during the build process.

·         After the BOOT.bin file is copied to the SD card on the host computer, insert the SD card in the target board SD card slot, set the jumper JP4 to SD mode and press the Reset button on the board. The board should start and run as per the logic.

·         For testing the communication, user may click on Simulation->Configure Simulation IO inside CASP. An interface appears as shown below

·         User can modify COM port and Ethernet IP as per his/her host setup and click Connect Device button. After successful connection user can check on ‘Online Data’ to view online data from the board as shown in above figure.