CASP Xilinx HLS Demonstration Project on Arty Z7-20 PL SoC Board

 

This project demonstrates how to create a Xilinx Vitis HLS IP targeted to Programmable Logic part of Xilinx SoC using CASP. Target platform selected is Digilent Arty Z7-20 SoC board.

 

Model

For this demonstration three logics are created in the model

·         Blink Logic - using a square wave generator (with one second period) connected to an on-board LED.

·         LED Brightness Control Logic - where in three push buttons are used to control brightness of three elements of a RGB LED independently. As the user clicks a push button corresponding LED brightness increases. After 20 counts the brightness resets to zero.

·         Shared Memory Communication Logic with Processing System (PS) – Digital inputs from two switches and analog inputs from three ADCs are combined into a data stream and copied to shared memory (write) that can be accessible by. Also, three analog outputs are generated from the shared memory (read) data stream to independently control the brightness of three elements of a RGB LED from PS. The communication method (Shared Memory) is selected from FPGAComm block parameter options.

 

Block Parameter Settings

User can view the individual block parameter settings by double clicking on each block.

 

Simulation Settings

Following are simulation setup options configured for current project. Settings that are not shown are left to defaults.

 

Work Flow

Pre-requisites:

·         Xilinx Vivado and Vitis HLS tools along with the target board drivers shall be installed

·         Target board should be connected to the host computer.

·         Xilinx Vitis HLS path shall be configured in CASP from CASP Settings -> Goto current board and right click on it -> Select ‘Addl. Board Variables’ option and enter the required path as shown below

 

 

Procedure:

·         Build the model by clicking on Build/Run button.

·         Build process may take several minutes. Build status can be viewed from CASP Build Window. User may need to disable ‘Suppress Information Messages’ under Simulation Setup -> Build tab to view the normal messages generated by Vitis HLS during the build process.

·         After completion of build, the Vitis HLS tool creates an IP for the current model ready to be used with Xilinx Vivado. This IP is located in the CASP current project build/bin directory. Refer Vitis HLS documentation for further details on HLS IP.

·         Run Xilinx Vivado application and open the project /hardware/xilinx/fpga/XC7Z020_TEMPLATE_PROJ/sam_proj1.xpr.

·         Include the HLS IP path we have just created using Vivado IP Catalog.

·         Open Vivado Block Design. Typical block design should look as shown in below figure. Older version of this IP already exists in the design as fgpa_main_0 block. Update it with the new HLS IP that we have created above.

vivado_block_design

·         In HLS IP, if shared memory is used for communicating with PS, connect shm0_PORTA of fpga_main_0 block to BRAM_PORTA of blk_mem_gen_shm block. By default the shared memory is mapped to MAXI GP0 at address 0x40000000 of PS through Vivado address editor.

·         Accordingly, shared memory inputs SW0 & SW1 are bit wise mapped to address 0x40000000, ADC channels A0, A1 and A2 are mapped to 0x40000004, 0x40000008, 0x4000000C respectively and shared memory outputs LED5-R, LED5-G, LED5-B are mapped to 0x40000000, 0x40000004 and 0x40000008 respectively.

·         MAXI GP1 at address 0x80000000 of PS is used to share additional input and output directly with PS without HLS IP. Accordingly, outputs LED1 & LED2 are bit wise mapped to address 0x80000000, LED3 is mapped to 0x80000008, inputs BTN0 to BTN3 are bit wise mapped to address 0x80000080 and ADC A3 is mapped to address 0x80000088,

·         User can make any modifications to the design and integrate with other IPs as per his/her requirement.

·         Follow Vivado work flow to generate final bit stream file for the design. After bit stream file is generated connect the target board to the host, set jumper JP4 to QSPI, remove jumper JP1 and upload the design with Vivado Hardware Manager.

·         This design can be integrated with PS executable file (.elf) into a BOOT.bin and can be copied to SD card for configuring PS and PL parts of the target board. Refer CaspPS project located in XC7Z020_TEMPLATE_PROJ directory for further details.