CASP Xilinx HLS Demonstration Project on Arty A7-100T FPGA Board

This project demonstrates how to create a Xilinx Vitis HLS IP targeted to Xilinx FPGAs using CASP. Target platform selected is Digilent Arty A7-100T FPGA board.

Model

For this demonstration three logics are created in the model

· Blink Logic - using a square wave generator (with one second period) connected to an on-board LED.

· LED Brightness Control Logic - where in three push buttons are used to control brightness of three elements of a RGB LED independently. As the user clicks a push button corresponding LED brightness increases. After 20 counts the brightness resets to zero.

· UART/Ethernet Communication Logic – Digital inputs from three switches and analog inputs from three ADCs are combined into a data stream and send to remote terminal (PC) through UART or Ethernet communication. Three analog outputs are generated from the received data stream to independently control the brightness of three elements of a RGB LED. The communication method (UART / Ethernet) is selected from FPGAComm block parameter options.

Block Parameter Settings

User can view the individual block parameter settings by double clicking on each block.

Simulation Settings

Following are simulation setup options configured for current project. Settings that are not shown are left to defaults.

Work Flow

Pre-requisites:

· Xilinx Vivado and Vitis HLS tools along with the target board drivers shall be installed

· Target board should be connected to the host computer.

· Xilinx Vitis HLS path shall be configured in CASP from CASP Settings -> Goto current board and right click on it -> Select ‘Addl. Board Variables’ option and enter the required path as shown below

Procedure:

· Build the model by clicking on Build/Run button.

· Build process may take several minutes. Build status can be viewed from CASP Build Window. User may need to disable ‘Suppress Information Messages’ under Simulation Setup -> Build tab to view the normal messages generated by Vitis HLS during the build process.

· After completion of build, the Vitis HLS tool creates an IP for the current model ready to be used with Xilinx Vivado. This IP is located in the CASP current project build/bin directory. Refer Vitis HLS documentation for further details on HLS IP.

· Run Xilinx Vivado application and open the project /hardware/xilinx/fpga/XC7A100T_TEMPLATE_PROJ/sam_proj1.xpr.

· Include the HLS IP path we have just created using Vivado IP Catalog.

· Open Vivado Block Design. Typical block design should look as shown in below figure. Older version of this IP already exists in the design as fgpa_main_0 block. Update it with the new HLS IP that we have created above.

· If UART is used for communication, connect uart_shm_PORTA of fpga_main_0 block to BRAM_PORTA of blk_mem_gen_uart block. And if Ethernet is used for communication, connect eth_shm_PORTA of fpga_main_0 block to BRAM_PORTA of blk_mem_gen_eth block.

· User can make any modifications to the design and integrate with other IPs as per his/her requirement.

· Follow Vivado work flow to generate final bit stream file for the design. After bit stream file is generated connect Arty A7-100T board to the host and upload the design with Vivado Hardware Manager.

· For testing the communication, user may click on Simulation->Configure Simulation IO inside CASP. An interface appears as shown below

· User can modify COM port and Ethernet IP as per his/her host setup and click Connect Device button. After successful connection user can check on ‘Online Data’ to view online data from the board as shown in above figure.