CASP supports interface with Verilog code through Veripool’s Verilator. It is available on native target with Desktop_MinGW_Verilog BSP. During build process, the veriog files are first converted to C files. The converted C files are used in CASP build pipeline for generating executables. User can add other verilog converts if required. Following procedure shall be adopted for using existing Verilog code.

·         Create a primary block as described in Create Primary Blocks section. Create block ports based on number of arguments in Verilog code. Generate block template code.

·         Call Verilog converted C files from the template code.

·         CASP provides a Verilog Demo block under /blocks/UserBlocks where user can re-use the block code as per his requirement.